WiSe is a Wi-Fi to Serial bridge..

• Wi-Fi module | ESP-12E/F/S (ESP8266 based)
• Serial UART | HW UART @ 3.3V TTL level
• RS-485 bus | Soft-UART, using MAX3485 transceiver
• Soft-UART at 38400 baud (typical) or alternate HW UART mapping
• 3.3V voltage regulator | LM117-3.3 (or AMS117-3.3) LDO (800mA~1A)

• WiSer (Climate edition) | html
  • w/ environment sensors (temperature ...)
• WiSer (Lighting edition) | html
  • for LED-strip controller
• WiSer (Control edition) | html
  • w/ buttons and OLED screen
  • option for high efficiency SMPS regulator (MPS1584/1593/2307)

• Serial bridge relays incoming data to all other active ports
• UART interface is also used for programming ESP8266 (when GPIO0 is tied low).
• RS485 transceiver is connected to alternate UART0 GPIOs, allowing to use either SW or HW UART.
• Note: ESP8266 HW UART has no support for RS485 DE signal. It must be generated from a timer.

ToBe Wise v1.0 is produced by OSH Park.

• Process | 2-layer prototype PCB service
• FR4 substrate
• 1 oz copper
• 1.6mm thickness
• ENIG (Immersion Gold) finish
• Dimensions | 0.76 x 1.01 inches (19.2 x 25.6 mm)
• Price (typ.) | 1.03€ per PCB ($3.80 for a set of 3 boards

• Schematics | pdf
• KiCad project files | zip
• Bill of Material | html
• Manufacturing files (OSH Park)
• PCB Layout | pdf
• Gerbers | zip

• ESP-12E | 170mA (Max, 11b tx), 80mA Average
• MAX3485 | 250mA (shorted outputs), 2.2mA (no load)
• SPI OLED | ~35mA (* WiSer only)

Pin	Name	Function	Comment
1	RST	In, PU	Chip reset, short J2 to keep module active or connect to external device
2	ADC	Analog In	External analog input
3	EN	In	Chip Enable, forced high (standby not supported)
4	GPIO16	n.c.	Not Used (Deep sleep wake up, connected -1kR- to RST on some modules)
5	GPIO14	n.c.	Not Used
6	GPIO12	n.c.	Not used
7	GPIO13	In	RS485 RX
8	VCC	Power	3.3V supply
9	CS0	n.c.	SPI CS0 (used by module flash)
10	MISO	n.c.	SPI MISO (used by module flash)
11	IO9	n.c.	SDIO DATA (used by module flash)
12	IO10	n.c.	SDIO DATA (used by module flash)
13	MOSI	n.c.	SPI MOSI (used by module flash)
14	SCLK	n.c.	SPI CLK (used by module flash)
15	GND	Power	Ground
16	GPIO15	Out, PD	RS485 TX, Boot Mode (pulled low at boot)
17	GPIO2	Out	Not used (ESP12F Module LED)
18	GPIO0	In	Boot mode (0:Uart, 1/float:SPI)
19	GPIO4	Out	RS485 DE
20	GPIO5	n.c.	Not used
21	RXD	In	UART RX
22	TXD	Out	UART TX

Rev.	Released	E.D.A.	Description	PCB Fab.	Prod. date	Qty	Notes
X-0			Prototype		2018-01-01	1x	#2
X-1			Adapter board		2018-12-04	1x	#4
v1.0	2017-10-09	KiCad 4.0.7	Initial version	OSH Park	2018-04-04	3x	#1

Index	Rev.	Location	Description	Fix
1	v1.0	top & bottom	Logo update	in v1.1
2	v1.0	J5-J6	Remove solder bridges	in v1.1
3	v1.0	J2	Use 0805 10k resistor	in v1.1
4	v1.0	J7	Add reset instead of 3V3, replace caps with boot jumper, add Vcc to 3V3 bypass 0R	in v1.1

SoftUart library

Soft UART implementation (requires HW timer, and GPIO Interrupt)

Web server

Web interface, w/ TLS support.

Source project

ESP8266 configuration is done by the following bootstraps:

• CH_PD (high) enable chip
• REST (high) enable chip
• GPIO15 (low) disable SDCard boot
• GPIO0 (high) SPI Flash boot, (low) Download code from Uart
• GPIO2 (high) Normal boot, Must use pull up

ESP8266 Boot Modes | html